Engineer's Folder
Our patented Finite-State Machine redefines addition as an iterative transformation of two input columns into two new output columns, reusing the same memory registers until the right column becomes zero and the left holds the result. It converges in logarithmic time, uses exactly one Half Adder per significant bit, and routes as a perfectly regular Manhattan grid. Array is Compute-In-Memory without exotic materials, without analog noise, and without dense 3D packaging — just standard edge-triggered flip-flops and CMOS logic.
We exist to make this architecture the default. For AI, for cryptography, for edge devices, for Bitcoin mining, for every workload that saturates on arithmetic throughput and memory bandwidth. We will license the IP, prove it in silicon, and partner with the fabs and design houses that are ready to leave the carry-over chain behind.
References for Technical Analysis
The energy and performance inefficiencies addressed by this patent are not new. They are the direct consequence of the Von Neumann Bottleneck, a fundamental limitation of the stored-program computer architecture that has been recognized and studied for decades. The cost of moving data is orders of magnitude higher than the cost of computing. This was established in seminal research and has been a central focus of computer architecture for several decades. The references cited below include landmark surveys, long-standing comparative analysis, and foundational studies that have stood the test of time, precisely because they correctly identified this primary obstacle to efficiency.
General Computer Architecture
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Researchers use 2D material to reshape 3D electronics for AI hardware
3D-Stacked CMOS Takes Moore’s Law to New Heights
A Little Bit of Everything. Code, Assembly, Arithmetic, Registers.
Arithmetic Logic Units (ALUs)
Notes on Computer Organization: Computer Arithmetic
Advanced Arithmetic Techniques
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Performance Analysis of Fast Adders Using VHDL
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Area, Delay and Power Comparison of Adder Topologies
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Performance Comparison of Some Synchronous Adders
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Design of Multiplication and Division Operation for 16 Bit Arithmetic Logic Unit (ALU)
Mahamad, Abd Kadir, Muhammad Ikmal Mohd Taib, Muhammad Najmi Zikry Nazri, Syazana Khairol Amali, and Muhamad Amirul Mohd Yusof @Md Jusoh1. 2020. Journal of Electronic Voltage and Application 1 (2): 46-54. https://publisher.uthm.edu.my/ojs/index.php/jeva/article/view/7219
An area-optimized N-bit multiplication technique using N/2-bit multiplication algorithm
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High Precision Integer Multiplication with a GPU Using Strassen’s Algorithm with Multiple FFT Sizes
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An Optimized Floating-Point Matrix Multiplication on FPGA
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Von Neumann Bottleneck
Computing's Energy Problem (and what we can do about it)
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Quantifying the Energy Cost of Data Movement in Scientific Applications
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Accelerating Dependent Cache Misses with an Enhanced Memory Controller
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Why Haven’t CPU Clock Speeds Increased in the Last Few Years?
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ASICs
Jim Keller’s Tenstorrent Wants To Compete With NVIDIA’s AI GPUs Using RISC-V Based AI CPUs
ASIC Design for Bitcoin Mining
Y. Sun, H. Yang, W. Zhang, and Y. Gu, University of Michigan, Ann Arbor, MI, USA, EECS 570 Final Report 2021. https://zwtaoumich.github.io/paper/EECS570_Final_Report.pdf
From Concept to Chip: The Art and Science of ASIC Design in Bitcoin Mining
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Custom ASIC Design for SHA-256 Using Open-Source Tools
Franck, Lucas Daudt, Gabriel Augusto Ginja, João Paulo Carmo, José A. Afonso, and Maximiliam Luppe. 2024. Computers 13, no. 1: 9. https://doi.org/10.3390/computers13010009
Compute-In-Memory
New Computing Hardware Needs a Theoretical Basis
A Full Spectrum of Computing-In-Memory Technologies
Zhong Sun, Shahar Kvatinsky, Xin Si, Adnan Mehonic, Yimao Cai and Ru Huang. Institute for Artificial Intelligence, School of Integrated Circuits, Peking University, Beijing Advanced Innovation Center for Integrated Circuits, Beijing 100871, China.
Research Progress in Architecture and Application of RRAM with Computing-In-Memory
Chenyu Wang, Ge Shi, Fei Qiao, Rubin Lin, Shien Wu, Zenan Hu, Nanoscale Advances, Volume 5, Issue 6, 2023, Pages 1559-1573, ISSN 2516-0230. https://www.sciencedirect.com/science/article/pii/S2516023023023742
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Recent Developments in Low-Power AI Accelerators: A Survey
Åleskog, Christoffer, Håkan Grahn, and Anton Borg. 2022. Algorithms 15, no. 11: 419. https://doi.org/10.3390/a15110419
Hardware Accelerators for Artificial Intelligence
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Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, and Yuan Xie. 2016. In Proceedings of the 43rd International Symposium on Computer Architecture (ISCA '16). IEEE Press, 27–39. https://doi.org/10.1109/ISCA.2016.13
China Makes Breakthrough in System-Integrated Memristor Computing-In-Memory Chips
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
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Microchip Breakthrough May Reshape the Future of AI
Defense One.
Intel Invests in ‘Groundbreaking’ AI Chip Architecture Startup
Swiss Researchers Develop First Large-Scale In-Memory Processor
The Uncertain Future of In-Memory Compute
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In-Memory Computing Challenges Come Into Focus
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Cerebras
Beyond Quantum: MemComputing ASICs Could Shatter 2048-bit RSA Encryption
Security Week.